1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to adjustment of timings at which address signals and data signals are latched.
2. Description of the Related Art
FIG. 1 is a block diagram of a command-input and address-input portion of a related-art semiconductor device.
As shown in FIG. 1, command-input signals /CAS (column address strobe), /RAS (row address strobe), /CS (chip select), and /WE (write enable) are input to input buffers 201 through 204. The input buffers 201 through 204 are current-mirror-type buffers, and produce a HIGH-level output or a LOW-level output depending on a comparison between an input signal and a reference voltage level.
The command signals output from the input buffers 201 through 204 are supplied to synchronization buffers 205 through 208, respectively, where synchronization is established between the command signals and a clock signal CLK. The command signals in synchronism with the clock signal CLK are supplied from the synchronization buffers 205 through 208 to a command decoder 209.
The command decoder 209 decodes the command signals /CAS, /RAS, /CS, and /WE so as to output command-decode signals. When the command signals /CAS, /RAS, /CS, and /WE are LOW, HIGH, LOW, and HIGH, respectively, for example, a data-read operation is selected, and the command-decode signals represent the data-read operation. When the command signals /CAS, /RAS, /CS, and /WE are LOW, HIGH, LOW, and LOW, respectively, for example, a data-write operation is selected, and the command-decode signals indicate this fact.
When either a data-write operation or a data-read operation is indicated, an address-input circuit 210 latches address signals at a timing triggered by the command-decode signals supplied from the command decoder 209. The address latched by the address-input circuit 210 is supplied to internal circuits. A control circuit 211 controls the internal circuits so as to achieve the operation which is indicated by the command-decode signals supplied from the command decoder 209. In FIG. 1, signal lines from the command decoder 209 to the address-input circuit 210 and the control circuit 211 are shown in a simplified manner. In actuality, a plurality of signal lines are provided for these paths.
The command decoder 209 is implemented by using a logic circuit of a relatively simple structure, but is designed to reduce an effect of skews between the command signals. Because of this, there is a problem in that a signal delay is relatively large in the command decoder 209. Assume that a two-input NAND circuit is used in the command decoder 209, and receives a first input signal and a second input signal, where the second signal is supposed to change from LOW to HIGH at the same timing at which the first signal changes from HIGH to LOW. If there is an unexpected delay in the change from HIGH to LOW in the first input signal, both signals maintain a HIGH level simultaneously during a short time period. The NAND circuit thus ends up outputting an erroneous signal level. In order to obviate this problem, a gate width of the transistors in the NAND circuit is made narrower, thereby slowing a change in the signal level. This prevents an erroneous signal level from appearing an output for a short time period.
When a signal delay at the command decoder 209 is elongated because of such a measure as described above to cope with signal skews, a timing at which the address-input circuit 210 latches the address signals is also delayed. Until the address signals are latched and stabilized, a data-write/read operation cannot be started. The delay in the command decoder 209 thus hinders an effort to increase operation speed of the semiconductor memory device.
Accordingly, there is a need for a semiconductor memory device which allows a timing of the address-signal input to be advanced in time so as to achieve high-speed operations.
Similar problems also exist with regard to timings of address-signal decoding, redundant checking, data-signal latching, and burst-length control.
Accordingly, there is a further need for a semiconductor memory device which advances these timings so as to achieve high-speed operations.